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Zilog
PRELIMINARY
Z90341
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z90341
DIGITAL TELEVISION CONTROLLER
FEATURES
s Part Number
Z90341
OTP ROM
64K x 16
RAM (Word)
1K x 16
Speed (MHz)
12
s s s s s s
Direct Closed Caption Decoding TV Tuner Serial Interface Customized Character Set Character Control Mode Directly Controlled Receiver Functions V-Chip Decode
s s s s
52-Pin Shrink DIP Package 4.5- to 5.5-Volt Operating Range Z89C00 RISC Processor Core 0C to +70C Temperature Range
GENERAL DESCRIPTION
The Z90341 is a member of Zilog's family of Digital Television Controllers designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The Z90341 features a powerful Z89C00 RISC processor core that controls on-board peripheral functions and registers using the standard processor instruction set. In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters. The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set. Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industrystandard I2C port. Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibility of text by adding a rightsided shadow effect to the characters. Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
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Zilog
PRELIMINARY
Z90341
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC HSYNC2 VSYNC /Reset CPU V3(B) RAM 1K x 16
Address ROM Addr Data OTP ROM 64K X 16
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6
CVI Port 17 Port 00 Port 05 Port 04
Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18
I2C SCL/MSCL2 SCD/MSCD2 MSCL1 MSCD1 OSD V1(R) V2(G)
Port 01/11 Port 02/12
PWM6
Register Addr/Data
ROM Data
Functional Block Diagram
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Zilog
PRELIMINARY
Z90341
PIN DESCRIPTION
Port 16/SCLK IRIN Port 0C Port 0B Port 0A Port 09 Port 0D Port 07/CSync Port 06/Counter Port 03 Port 02/I2CSSC Port 01/I2CSSD CVI/ADC0 LPF AGNDF ADC5 Port 04/ADC4 Port 05/ADC3 Port 00/ADC2 Port 17/ADC1 AGND AVCC Port0F/Stransp V3/B V2/B V1/B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 Port15/B1 Port14/B0 Port13/G1 Port18/G0 Port08/R1 Port10/R0 PWM6/Hsync2 PWM5 PWM4 PWM3 PWM2 PWM1 AGNDX VCC GND XTAL2 XTAL1 /Reset I2MSC1 I2MSD1 Port 0E Port11/I2CMSC2 Port12/I2CMSD2 VSync HSync Blank
Z90341
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
52-Pin Shrink DIP Configuration
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Zilog
PRELIMINARY
Z90341
PIN DESCRIPTION Z89313
Pin Name VCC , AVCCa GND, AGND, AGNDF, AGNDXb IRIN ADC[5:1] Z90341 52-Pin 39,22 38,21,15,40 2 16,17,18,19,20 Configuration Direction PWR PWR I AI
Function +5 V 0V Infrared Remote Capture Input 4-Bit Analog-to-Digital Converter Input 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports
Reset - - I I
PWM[6:1] Port0[F:0]
46,45,44,43,42,41 23,32,7,3,4,5,6,48,8,9,18, 17,10,12,11,19 49,20,1,52,51,50,30, 31,47 11,31,34 12,30,33 36 37 14 28,46 29 35 24,25,26 27 23 -
O B
O I
Port1[8:0] SCL SCD XTAL1 XTAL2 LPF HSYNC VSYNC /RESET V[3:1] Blank Semi transparent SCLK
Bit Programmable Input/Output Ports I2C Clock I/O I2C Data I/O Crystal Oscillator Input Crystal Oscillator Output Loop Filter H_Sync V_Sync Device Reset OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Semi transparent Output Internal Processor SCLK
B BOD BOD AI AO AB B B I O O O O
I
I O O I I I O O
Notes: Please refer to pin-out diagram for shared pin numbers.
a) AVCC is for the reference voltage of the ADC input.
b) AGND is for the reference ground of the ADC input. AGNDF is for LPF ground, and AGNDX is for XTAL circuit ground.
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PRELIMINARY
Z90341
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V
VCC = 5.25 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10pf Load Limit 2.10 V 0.3 V 1.75 V 0.3 V 1.28 V 0.30 V 0.0 + 0.3V < 50 ns
Setting Time
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75 V
VCC = 4.75 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10pf Load Limit 1.90 V 0.30 V 1.60 V 0.30 V 1.20 V 0.30 V 0 V + 0.3 V < 50 ns
Setting Time
Z9034X
10 Mohm
68pF
32.768k
XTAL1
XTAL2 27k
560pF
32K Oscillator Recommended Circuit
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Zilog
PRELIMINARY
Z90341
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VID VIA VO IOH IOH IOL IOL TA TS Parameter Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature Min 0 -0.3 -0.3 -0.3 Max 7 VCC +0.3 VCC +0.3 VCC +0.3 -10/-1a -100 20/1b 200 70 150 Units V V V V mA mA mA mA C C Conditions Digital Inputs Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output One Pin All Pins One Pin All Pins
0 -65
Notes: a) 1 mA max. when output pad impedance is 600 . b) 1 mA max. when output pad impedance is 600 .
DC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz
Symbol VIL VIH VOL VOH VXL VXH VHY IIR IIL ICC ICC1 ICC2 Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current Input Leakage Supply Current Supply Current Supply Current Min 0 0.6 VCC Max 0.2 VCC VCC 0.4 VCC -0.9 0.3 VCC VCC -2.0 3.0 -3.0 0.75 150 3.0 100 300 40 Typical 0.4 3.6 0.16 4.75 1.0 3.5 0.5 90 0.01 60 100 5 Units V V V V V V V A A mA A A @ IOL = 1 mA @ IOL = 0.75 mA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V @ 0 V and VCC Sleep Mode @ 32 KHz Stop Mode Conditions
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PRELIMINARY
Z90341
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol TP C TRC,TFC TD POR Parameter Input Clock Period Clock Input Rise and Fall Power On Reset Delay Min 16 0.8 Max 100 Typical 32 12 1.2 Units s s s Depends on Crystal Note
AC CHARACTERISTICS* TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol TW RES TD HS TD VS TD ES TD OS TW HVS Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width Min 5.5 0.15 -12 20 Max 5TPC 12.5 1.5 +12 44 2.0 Typical 11 1.0 0 32 0.5 Units s S ms s s s
Notes: All timing of the I2C bus interface are defined by related specifications of the I2 C bus interface.
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
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